1. Field of the Invention
The present invention relates to a semiconductor device including a redundancy circuit, and a method of operation thereof.
2. Description of the Background Art
In accordance with increase in the integration density of semiconductor memory devices, particularly of dynamic type RAMs (DRAM), the consumption power during a stand-by operation is ever increasing. Particularly in a DRAM, stored information is maintained by rewriting/rereading the stored data even during a stand-by state, so that there is a limit in reducing the consumption power during a stand-by state in principle.
It is a critical issue to achieve any reduction in the consumption power during a stand-by state in a system that uses a great amount of DRAM.
Increase in the integration density also causes increase in the occurrence of defective memory cells.
In order to compensate for generation of error due to such defective memory cells, the approach by the so-called redundancy circuit is carried out where a column of memory cells in which a defective memory cell is present is replaced with an auxiliary column of memory cells or the like.
By virtue of such replacement, the basic operation of reading/writing data of a memory cell is carried out smoothly. However, a leakage current path of the defective portion is still present even when the relevant defection is repaired by the redundancy circuit. This means that the consumption power during a stand-by state of the DRAM is further increased.
The above circumstance will be described in detail with reference to FIG. 18 showing a structure of a conventional DRAM.
The operation of each component will first be described briefly.
In a Y address comparator circuit 38, an address detected as including a defective bit at the time of previous testing is stored in a non-volatile memory such as a fuse circuit.
When an externally applied address signal 40 does not match the above identified address including a defective bit, a column select line drive circuit 34, for example, is activated, whereby a column select line (referred to as "CS line" hereinafter) 24 is pulled up to an H level (logical high).
By an I/O gate 19 of a bit line pair group unit 102 (corresponding to I/O gate 18 in bit line pair group unit 100), a pair of bit lines BL3, /BL3 is connected to a data input/output line 20.
The potential difference of bit line pair BL3, /BL3 is amplified by a sense amplifier 17 according to stored information in a memory cell connected thereto and selected by a signal of a word line not shown.
By the above operation, information in a memory cell is externally read out.
If there is a shorting portion 200 between bit line BL1 and the ground level, data cannot be read/written with respect to a memory cell connected to that bit line.
In this case, the defective bit line is replaced with an auxiliary bit line. In general, this replacement is carried out not in the unit of a bit line, but in the unit of a bit line pair group connected by a CS line.
More specifically, the address of CS line 22 corresponding to bit line pair group unit 100 to which the defective bit line BL1 belongs is preprogrammed in a Y address comparator circuit 38.
Externally applied address 40 is compared with this programmed defective address by Y address comparator circuit 38. When the two values match each other, a signal (SE signal) activating a space column decoder is applied to a CS line drive circuit 36, whereby a bit line pair group unit 104 formed of spare bit line lines of a spare BL1 and a spare /BL1 is selected.
At the same time, a signal (NED signal) inactivating the CS line associated with the defective bit line BL1 is applied to a CS line drive circuit 32.
Thus, replacement of a defective bit is carried out. There is no problem in the basic operation of the memory cell.
However, as disclosed in U.S. Pat. No. 4,663,584, for example, the bit line pair is precharged to the level of a potential V.sub.BL supplied by a bit line potential generation circuit (not shown) in the chip prior to an amplify operation of sense amplifier 16 according to the data in the memory cell. Here, potential V.sub.BL is set to 1/2 V.sub.cc where V.sub.cc is the potential supplied from a power supply 2.
The value of V.sub.BL is not limited to 1/2 V.sub.cc, and an arbitrary value can be set.
A first power supply line S2P connected to power supply 2 bias a switching transistor 10 and leading to a sense amplifier, and a second power supply line S2N connected to ground via a switching transistor 12 and leading to a sense amplifier are also precharged as the bit line pair. Each of first and second power supply lines S2P and S2N is generally referred to as line S2 hereinafter.
Therefore, a first leakage current path 202 and a second leakage current path 204 are generated due to the presence of shorting portion 200. In first leakage current path 202, the current from the supply line of the potential of the bit line potential generation circuit through a bit line equalize circuit 14 coupling the pair of bit lines BL1 and /BL1 in common to potential V.sub.BL leaks through bit line BL1. In second leakage current path 204, the current from a S2 line equalize circuit 4 coupling line S2 in common to potential V.sub.BL leaks through line S2, sense amplifier 16, and bit line BL1.
As a result, the problem that the stand-by current becomes larger in the memory cell unit occurs.
There is also a disadvantage that the operation margin with respect to V.sub.BL is significantly reduced since potential V.sub.BL becomes lower than the design value.
This will be described according to the timing chart of FIG. 19 thereof.
At time t.sub.0, all the pairs of bit lines should be precharged to the level of potential V.sub.BL. However, the potential of bit line pair BL1, /BL1 associated with the defective bit is lower than potential V.sub.BL (=1/2 V.sub.cc) due to leakage current.
Line S2 of the sense amplifier is also lower than precharge voltage V.sub.BL due to leakage current. It is to be noted that reduction in the potential of line S2 influences the operation of all the sense amplifiers connected in common to line S2.
Following the transition of a line address strobe signal /RAS to an L level from an H level at time t.sub.2, an internal signal BLEQ is pulled down to an L level from an H level at time t.sub.3, whereby the bit line pair is electrically isolated.
Similarly, S2 line equalize circuit 8 is turned off, whereby the pair of line S2 is electrically isolated.
Then, at time t.sub.5, switching transistors 10 and 12 are turned on in response to signals /SOP and SON, respectively, whereby sense amplifier 16 is activated.
As a result, the pair of bit lines BL1, /BL1 and the pair of spare lines BL1 and /BL1 has one potential driven to the level of V.sub.cc and the other to the level of ground according to the stored information in the memory cells selected correspondingly.
At the transition of signals NED and SE to an H level from an L level at time t.sub.8, CS1 line 22 maintains its inactive state, and spare CS line 26 is activated. As a result, data is provided to data input/output line (I/O line (20).
At time t.sub.12, signal /RAS is driven to an H level from an L level. At time t.sub.13, signal BLEQ is driven to an H level from an L level.
At the same time, the sense amplifier attains an inactive state by signals /SOP and SON. In response to signal BLEQ, the bit line pair is precharged to the level of V.sub.BL again. However, the potential of bit line pair BL1, /BL1 is lowered by leakage current. Also, the potential of line S2 is reduced.
Thus, the potential of line S2 prior to activation of the sense amplifier is lower than V.sub.BL (=1/2 V.sub.cc) due to leakage current. The resulting reduction in the V.sub.BL margin has become a serious problem in recent years in accordance with increase of the capacity of the memory.
Due to increase in the memory capacity and microminiaturization in the device size, reduction in the power supply voltage is required from the standpoint of reliability. Therefore, the problem of degradation in the V.sub.BL margin due to reduction in voltage is further aggravated due to reduction in V.sub.BL by a leakage current path.
A conventional semiconductor memory device has the problem that the actual stand-by current of a memory cell portion is increased and the operation margin with respect to potential V.sub.BL is degraded due to a leakage current of a defective portion.